Research in 3D integration has attracted researchers from industry as well as academia due to its benefits over 2D architecture such as better performance, lower power consumption, small form factor and support for heterogeneous technology integration. Furthermore, various 3D memory architectures have been proposed to cater to the high bandwidth requirement at low power. However, due to its higher power density and reduced heat dissipation properties, thermal challenges are expected to cause significant concerns in the promising 3D integration technology. We aim to investigate system-level thermal aware data/task mapping policies for 3D memory architectures.